1. Field of Invention
The present invention pertains to the field of processors. More particularly, this invention relates to address translation registers in a processor.
2. Art Background
A computer system typically includes a processor and a main memory. The main memory of a computer system usually stores instructions and data. A processor typically reads the instructions from the main memory and executes the instructions. The execution of the instructions may cause the processor to read data from the main memory and/or write data to the main memory.
A processor typically has a processor architecture which includes a virtual address space for referencing instructions and data. The main memory, on the other hand, usually has a memory architecture which includes a physical address space for storing instructions and data. Typically, the physical address space of a main memory is much smaller than the virtual address space of a processor. In addition, the physical address space of a main memory may have discontinuities in its range of valid addresses.
As a consequence, computer systems commonly include address translation mechanisms for converting the virtual addresses used by a processor to the appropriate physical addresses for the main memory. Such address translation mechanisms typically enable the implementation of virtual memory mechanisms and allow very large processes with large data structures to be executed using a relatively small main memory.
An address translation mechanism for a computer system typically includes a page directory which is stored in main memory. A page directory usually includes a set of entries each of which contains information for translating virtual addresses to the appropriate physical addresses. In addition, prior processors commonly include translation look-aside buffers (TLBs) that hold a subset of the entries of the page directory. A TLB may be viewed as a cache of page directory entries. TLBs usually enhance the speed of a processor by avoiding main memory accesses to the page directory during translation of virtual addresses to physical addresses.
It is usually desirable that a TLB in a processor be implemented such that a TLB lookup can be performed in a single processor cycle or relatively few processor cycles. Prior processors typically achieve such TLB lookup speeds by limiting the storage capacity of a TLB. Unfortunately, such limited capacity usually increases the likelihood of a TLB miss which in turn causes a very slow access to the page directory in the main memory. Such main memory accesses during address translation usually slow the performance of a processor. In addition, a TLB in a processor can become polluted during context switches among processes. Unfortunately, such pollution of a TLB usually increases the likelihood of a TLB miss and a resulting slow main memory access to the page directory.
A processor is disclosed having one or more address translation registers for holding translation information that enables translations from virtual addresses to physical addresses. The address translation registers may be allocated to a set of logical areas of a process and the logical areas may be allocated to physical pages so as to enhance a likelihood that translation information for the process will be available in the address translation registers. The address translation registers are saved and restored during context switches. The address translation registers may be used with or without translation look-aside buffers.
Other features and advantages of the present invention will be apparent from the detailed description that follows.